I've been accused (by my wife) of being a bit slow in the morning, so forgive me if I missed it -- but where is the news about the MMU? I followed the links to the ARM announcement and the Ars Technica article, and I didn't see it (I searched for MMU in both pages).
It seems too good to be true. Just wondering if I can read the news somewhere.
DGentry
· 2 months ago
Indeed, as pointed out I missed the Cortex-M parts altogether. I've added an update to the post referencing these comments, and linking to the Cortex-Ms.
Brooks Moses
· 2 months ago
You seem to have somehow missed the entire Cortex-M range! The most recent ARM architecture is split into three families -- Cortex-A (for "applications"), Cortex-R (for "realtime"), and Cortex-M (for "mobile", or possibly "embedded"). All of the Cortex-A series have MMUs and can run Linux, because that's their reason for existence. The Cortex-M series, however, do not; their reason for existence is competition with the 8-bit and 16-bit microprocessor world.
In any case, the Cortex-M0 is substantially smaller than the Cortex-A5, at around 12k gates total, and I would guess that the Cortex-M3 is a fair bit smaller as well. The A5 is merely the smallest in the Cortex-A range, and rather smaller than the current Cortex-A8.
(Dave, the news about the MMU is in the diagram that Denton reproduced. But, in any case, the whole purpose of this chip is to run Linux-like things.)
Dave Cason
· 2 months ago
Hi Brooks,
Thanks for your comment. I saw the picture of the A5 with the MMU, but the text was very explict that all ARM cores (regardless of price) would feature an MMU.
Since I'm currently hip-deep in a dual-core M3-M0 design, I practically started speaking in tongues when I read that the lowly M0 (which doesn't even have the option of an MPU if I recall) would get an MMU. There are some things we do in our kernel that would greatly benefit from an MMU, so I thought we just won the lottery.
I don't expect that many M3, let alone M0, users would be clawing for a full-blown MMU, that's why I couldn't believe it.
Brooks Moses
· 2 months ago
Oh, I think I misunderstood your question; I thought you were asking about where the news about the Cortex-A5 in particular having an MMU came from. Sorry about that!
DGentry
· 2 months ago
You're right, I missed the Cortex-M. On the Cortex-A5 page I saw the ARM11, ARM10, ARM7, etc but did not notice the "Embedded Processors" link where the Cortex-M series resides. The last ARM I worked with ran uClinux; to me, the Cortex-A5 with a full Linux kernel is a wonderful thing.
I've added an update at the bottom of the post, referencing these comments and linking to the Cortex-M.
Brooks Moses
· 2 months ago
Oh, definitely -- having had a passing acquaintance with uClinux, I would certainly agree that supporting a full Linux kernel is a great improvement! I don't mean my comment to take away from that -- and it's true that every ARM core that you might run more than the barest RTOS on will have an MMU, and that itself is significant.
(The Cortex-M range is, I gather, trying to do a similar thing for people who've been used to 8-bit or 16-bit systems, and for whom being able to have a 32-bit system is a similar wonderment. It's an interesting trend.)
All Comments
It seems too good to be true. Just wondering if I can read the news somewhere.
In any case, the Cortex-M0 is substantially smaller than the Cortex-A5, at around 12k gates total, and I would guess that the Cortex-M3 is a fair bit smaller as well. The A5 is merely the smallest in the Cortex-A range, and rather smaller than the current Cortex-A8.
(Dave, the news about the MMU is in the diagram that Denton reproduced. But, in any case, the whole purpose of this chip is to run Linux-like things.)
Thanks for your comment. I saw the picture of the A5 with the MMU, but the text was very explict that all ARM cores (regardless of price) would feature an MMU.
Since I'm currently hip-deep in a dual-core M3-M0 design, I practically started speaking in tongues when I read that the lowly M0 (which doesn't even have the option of an MPU if I recall) would get an MMU. There are some things we do in our kernel that would greatly benefit from an MMU, so I thought we just won the lottery.
I don't expect that many M3, let alone M0, users would be clawing for a full-blown MMU, that's why I couldn't believe it.
I've added an update at the bottom of the post, referencing these comments and linking to the Cortex-M.
(The Cortex-M range is, I gather, trying to do a similar thing for people who've been used to 8-bit or 16-bit systems, and for whom being able to have a 32-bit system is a similar wonderment. It's an interesting trend.)